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async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
async_transmitter
- RS232串口发送模块，verilog编写，可综合-async_transmitter verilog module
S7_PS2_RS232
- 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
rs232
- 异步串行传输的verilog hdl 功能文件以及测试文件-The verilog hdl source and the testbench of asynchronous serial transmission
S7_PS2_RS232
- 基于verilog语言PS2接口和RS232接口的实现-PS2 based on verilog language interface and RS232 interface implementation
PS2andRS232
- 基于Verilog语言PS2接口和RS232接口的实现 有文档说明,工程实例.可用来学习Verilog语言.-Based on Verilog Language PS2 interface and RS232 interface implementation are documented, project examples. Can be used to learn the Verilog language.
uart
- RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
rs232
- RS232的串口控制器，本程序中的每个小模块都有与之对应的testbench，模块清晰，实现结构简单。很适合Verilog编程初学者来练习！-RS232 serial port controller, the program has a small module for each corresponding testbench, module definition, to achieve simple structure. Verilog programming is suitable for
PS2RS232
- 这是关于PS2和rs232串口的代码，verilog的，是深入了解串口的好的学习实例。-good code about rs232 and ps2
RS232_NIOS_Verilog
- 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
rs232
- 使用VERILOG 代码实现的RS232 发送功能，接收一个字符马上回送回来-The RS232 using VERILOG code sending, receiving and sent back immediately return a character
FPGAandRS232-485VerilogSourcecode
- FPGA串行通信口RS232-485构建，RS232和485有选择控制，源程序基于QuartusII6.0用Verilog语言撰写。-FPGA serial communication port RS232-485 build, RS232 and 485 to selectively control, source-based QuartusII6.0 written in Verilog language.
rs232
- 这是用verilog语言写的串口自收发实验的源代码，通过板子实验，采用分层模块化设计，代码大家请仔细阅读-It is written in verilog serial transceiver test from the source code through the board experiments, a stratified modular design, code, we can slowly digest
my_uart1_VERILOG_using-PLL
- Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using P
RS232
- verilog语言编写的串口收发器，可实现发送什么接受什么的功能，简单修改即可实现想要的功能-verilog UART
RS232
- 利用verilog开发的串口程序，比较基本，包含完整的工程-Use the verilog development of the serial procedures more basic, including complete engineering
UART-RS232
- 用verilog语言描述了uart串口通信实验-Verilog language descr iption of the uart serial communication experiment
rs232
- 一种verilog实现rs232的方法~没啥好说的-A verilog implementation rs232 methods to nothing to say
RS232
- RS232与电脑串口的通信控制代码，verilog hdl代码，里面包括完整的ISE工程-RS232 and computer serial communication control code, verilog hdl code, which includes a complete ISE works
uart_232
- RS232的verilog控制程序，8位数据传输，奇校验，一个停止位，已经过singnaltap验证-RS232 verilog control procedures, the eight data transmission, odd parity, one stop bit, verification has been singnaltap